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An optimized implementation of a fault-tolerant clock synchronization circuitA fault-tolerant clock synchronization circuit was designed and tested. A comparison to a previous design and the procedure followed to achieve the current optimization are included. The report also includes a description of the system and the results of tests performed to study the synchronization and fault-tolerant characteristics of the implementation.
Document ID
19950017962
Acquisition Source
Legacy CDMS
Document Type
Technical Memorandum (TM)
Authors
Torres-Pomales, Wilfredo (NASA Langley Research Center Hampton, VA, United States)
Date Acquired
September 6, 2013
Publication Date
February 1, 1995
Subject Category
Computer Systems
Report/Patent Number
NAS 1.15:109176
NASA-TM-109176
Report Number: NAS 1.15:109176
Report Number: NASA-TM-109176
Accession Number
95N24382
Funding Number(s)
PROJECT: RTOP 505-64-10-13
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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