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Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) DevicesSpace applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.
Document ID
20150018112
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
Authors
Berg, M. (ASRC Federal Space and Defense Greenbelt, MD, United States)
Kim, H. (ASRC Federal Space and Defense Greenbelt, MD, United States)
Phan, A. (ASRC Federal Space and Defense Greenbelt, MD, United States)
Seidleck, C. (ASRC Federal Space and Defense Greenbelt, MD, United States)
LaBel, K. (NASA Goddard Space Flight Center Greenbelt, MD, United States)
Pellish, J. (NASA Goddard Space Flight Center Greenbelt, MD, United States)
Campola, M. (NASA Goddard Space Flight Center Greenbelt, MD, United States)
Date Acquired
September 17, 2015
Publication Date
July 13, 2015
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN24990
Meeting Information
Meeting: 2015 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2015)
Location: Boston, MA
Country: United States
Start Date: July 13, 2015
End Date: July 17, 2015
Sponsors: Institute of Electrical and Electronics Engineers
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Field Programmable Gate Array (FPGA)
and Markov Chains
Availability
Mean time to failure (MTTF)
Single event upset (SEU)
Triple Modular Redundancy (TMR)

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