High performance pipelined multiplier with fast carry-save adderA high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.
Document ID
19940004375
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Wu, Angus (Washington State Univ. Pullman, WA, United States)
Date Acquired
August 16, 2013
Publication Date
November 6, 1990
Publication Information
Publication: Idaho Univ., The 2nd 1990 NASA SERC Symposium on VLSI Design