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A set-associative, fault-tolerant cache designThe design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.
Document ID
19940017258
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Lamet, Dan (Idaho Univ. Moscow, ID, United States)
Frenzel, James F. (Idaho Univ. Moscow, ID, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1992
Publication Information
Publication: The 1992 4th NASA SERC Symposium on VLSI Design
Subject Category
Computer Programming And Software
Accession Number
94N21731
Funding Number(s)
CONTRACT_GRANT: NAGW-1406
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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