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A real time correlator architecture using distributed arithmetic principlesA real time correlator design based on the principles of Distributed Arithmetic (DA) is described. This design is shown to be more efficient in terms of memory requirement than the direct DA implementation, especially when the number of coefficients is large. Since the proposed architecture implements the sum of product evaluation, it can be easily extended to finite and infinite response filters. Methods to further reduce the memory requirements are also discussed. A brief comparison is made between the proposed method and different DA implementations.
Document ID
19940017261
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Premkumar, A. Benjamin
(Nanyang Technological Inst.)
Srikanthan, T.
(Nanyang Technological Inst.)
Date Acquired
September 6, 2013
Publication Date
January 1, 1992
Publication Information
Publication: Idaho Univ., The 1992 4th NASA SERC Symposium on VLSI Design
Subject Category
Computer Operations And Hardware
Accession Number
94N21734
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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