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A very high speed hard decision sequential decoder.Description of a 40-megabit-per-second hard decision sequential decoder which employs the fastest commercially available digital integrated circuits - MECL III. With this decoder an internal computational rate of 70,000,000 computations per second has been achieved. The computational efficiency of the decoding algorithm has been improved by incorporating two modifications to the Fano algorithm - namely, 'double quick threshold loosening' and 'diagonal steps.' On the basis of preliminary results, an output error rate of 0.00001 can be achieved with E sub b/N sub zero less than 5.4 dB at data rates up to 40 megabits per second. The very high internal operating speed of the decoder represents a factor of five increase in speed over any previous sequential decoder.
Document ID
19730030596
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Gilhousen, K. S.
(Linkabit Corp. San Diego, Calif., United States)
Lumb, D. R.
(NASA Ames Research Center Moffett Field, Calif., United States)
Date Acquired
August 7, 2013
Publication Date
January 1, 1972
Subject Category
Computers
Meeting Information
Meeting: NTC ''72; National Telecommunications Conference
Location: Houston, TX
Start Date: December 4, 1972
End Date: December 6, 1972
Accession Number
73A15398
Distribution Limits
Public
Copyright
Other

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