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A wide bandwidth CCD buffer memory systemA prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.
Document ID
19780023348
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Siemens, K.
(Bell-Northern Research Ltd. Ottawa Ontario, Canada)
Wallace, R. W.
(Bell-Northern Research Ltd. Ottawa Ontario, Canada)
Robinson, C. R.
(Bell-Northern Research Ltd. Ottawa Ontario, Canada)
Date Acquired
August 9, 2013
Publication Date
June 1, 1978
Publication Information
Publication: AGARD Impact of Charge Coupled Devices and Surface Acoustic Wave Devices on Signal Process. and Imagery in Advanced Systems
Subject Category
Computer Operations And Hardware
Accession Number
78N31291
Funding Number(s)
CONTRACT_GRANT: NAS1-13507
Distribution Limits
Public
Copyright
Other
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