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Improved process control for VMOS FET'sMethod is applied in middle of fabrication process: (a) after mask region is formed, diffused-boron region is etched; (b) etching is left incomplete for ion implantation; (c) boron ions are implanted into region to define accurately crucial geometry of V-groove; (d) groove is etched to completion, forming two well-defined diffusion regions that serve as source and drain of transistor. Remaining process is conventional.
Document ID
19790000563
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Jhabvala, M. D.
Date Acquired
August 10, 2013
Publication Date
June 1, 1980
Publication Information
Publication: NASA Tech Briefs
Volume: 4
Issue: 4
ISSN: 0145-319X
Subject Category
Fabrication Technology
Report/Patent Number
GSC-12515
Accession Number
79B10563
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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