A microprocessor based communications multiplexer/concentrator

In the past communications concentrators have been designed using mini-computers. In this work a design for a high speed concentrator (in the megabits range) is developed using the 3000 series bit slice microprocessor. The proposed concentrator realizes the functions of multiplexing of the data arriving on the low speed lines, demultiplexing of the data arriving on the high speed line, including canned responses and code conversion. The basic system hardware configuration and the principles of operation of the multiplexing and the demultiplexing subsystems are presented. The software for these two functions are also presented. Using queueing theory, an estimate of the required buffer size is provided. Possible areas of further improvement are also indicated.