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Implementing a bubble memory hierarchy systemThis paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.
Document ID
19790065329
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Segura, R.
(NASA Langley Research Center Hampton, VA, United States)
Nichols, C. D.
(NASA Langley Research Center Hampton, Va., United States)
Date Acquired
August 9, 2013
Publication Date
July 1, 1979
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: Institute of Electrical and Electronics Engineers and American Institute of Physics, Joint Intermag-Magnetism and Magnetic Materials Conference
Location: New York, NY
Start Date: July 17, 1979
End Date: July 20, 1979
Accession Number
79A49342
Distribution Limits
Public
Copyright
Other

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