A bubble memory moduleA bubble memory module design providing flexibility for many user applications in spacecraft data recording is described. The memory module can be used with user-designed controllers with the memory organization determined by the application. Asynchronous data rates from zero to 1.33 Mbits/sec at minimum power are accomplished by using 8-chip memory cells with 100 K bit serial chips. The memory module is expandable from a 4 x 2 cell matrix to a 4 x 16 cell matrix corresponding to an expandable capacity of 6.55 M to 52.4 M bits. The module's design, utility in various memory systems, and user clocking scheme are described.
Document ID
19800048657
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Hayes, P. J. (NASA Langley Research Center Hampton, VA, United States)
Segura, R. (NASA Langley Research Center Hampton, VA, United States)
Stermer, R. L., Jr. (NASA Langley Research Center Hampton, Va., United States)
Bohning, O. D. (Rockwell International Corp. Anaheim, Calif., United States)
Date Acquired
August 10, 2013
Publication Date
April 1, 1980
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: International Magnetics Conference
Location: Boston, MA
Start Date: April 21, 1980
End Date: April 24, 1980
Sponsors: Institute of Electrical and Electronics Engineers