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A microprocessor based satellite borne packet switchDesign considerations applicable to a space-borne single microprocessor based packet switch are identified. These include system architecture decisions and microprocessor selection. The division of tasks among different subroutines is discussed. The primary design criterion is to maximize throughput. The extension to a multi-satellite network is discussed. The maximum throughput attainable is derived. A queue theoretic model has been developed and expressions for average response times and average queue sizes are obtained. A number of graphs showing the effect of various design parameters on the average response time and the average queue sizes are presented.
Document ID
19810037486
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Crist, S. C. (Clarkson Coll. of Technology Potsdam, NY, United States)
Burnell, J. F. (Clarkson Coll. of Technology Potsdam, NY, United States)
Arozullah, M. (Clarkson College of Technology Potsdam, N.Y., United States)
Date Acquired
August 11, 2013
Publication Date
January 1, 1979
Subject Category
Communications And Radar
Meeting Information
Meeting: NTC ''79; National Telecommunications Conference
Location: Washington, DC
Start Date: November 27, 1979
End Date: November 29, 1979
Accession Number
81A21890
Funding Number(s)
CONTRACT_GRANT: NSG-3191
Distribution Limits
Public
Copyright
Other

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