Test vectors development and optimization for a microprocessorThis paper describes a method for generating and optimizing test vectors for a microprocessor, with the aid of a fault simulator implemented entirely by hardware. The development and optimization of test vectors has been done on a tester, with the fault simulator plugged directly into the test head. The fault simulator is capable of automatically injecting over a thousand single or multiple stuck faults in the sequential and combinatorial parts of the microprocessor. The test vectors developed by a programmer working interactively with the tester were applied through the tester to the fault simulator, and the percent of faults detected was measured. The vectors were developed and optimized for the 1802 microprocessor, with the objective of detecting 100% of the single stuck faults with a minimum set of vectors. Experimental results show that 99.7% of the single stuck faults are being detected with approximately 14,000 vectors.
Document ID
19820044366
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Timoc, C. C. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Hess, L. M. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Stott, F. R. (California Institute of Technology, Jet Propulsion Laboratory, Pasadena CA, United States)
Date Acquired
August 10, 2013
Publication Date
January 1, 1980
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: In: AUTOTESTCON ''80; International Automatic Testing Conference