Logic Simulator Program

The source code for the SPICE 2 program was deblocked in order to isolate and compile the subroutine in an effort to provide a software simulation of discrete and combinatorial electronic components. Incompatibilities between the UNIVAC 1180 FORTRAN and the Sigma V CP-V FORTRAN 4 were resolved. The SPICE 2 model is to be used to determine gate and fan-out delays, logic state conditions, and signal race conditions for transistor array elements and circuit logic to be patterned in the (SPI) 7101 CMOS silicon gate semicustom array. The simulator is to be operable from the CP-V time sharing terminals.