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A Systolic VLSI Design of a Pipeline Reed-solomon DecoderA pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.
Document ID
19840011563
Acquisition Source
Legacy CDMS
Document Type
Other
Authors
Shao, H. M. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Truong, T. K. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Yuen, J. H. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Reed, I. S. (Univ. of Southern California)
Date Acquired
August 11, 2013
Publication Date
February 15, 1984
Publication Information
Publication: The Telecommun. and Data Acquisition Rept.
Subject Category
Computer Operations And Hardware
Accession Number
84N19631
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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IDRelationTitle19840011553Collected WorksThe Telecommunications and Data Acquisition Report
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