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Hierarchical Design and Verification for VLSIThe specification and verification work is described in detail, and some of the problems and issues to be resolved in their application to Very Large Scale Integration VLSI systems are examined. The hierarchical design methodologies enable a system architect or design team to decompose a complex design into a formal hierarchy of levels of abstraction. The first step inprogram verification is tree formation. The next step after tree formation is the generation from the trees of the verification conditions themselves. The approach taken here is similar in spirit to the corresponding step in program verification but requires modeling of the semantics of circuit elements rather than program statements. The last step is that of proving the verification conditions using a mechanical theorem-prover.
Document ID
19840017255
Acquisition Source
Legacy CDMS
Document Type
Other
Authors
Shostak, R. E.
(SRI International Corp. Menlo Park, CA, United States)
Elliott, W. D.
(SRI International Corp. Menlo Park, CA, United States)
Levitt, K. N.
(SRI International Corp. Menlo Park, CA, United States)
Date Acquired
August 12, 2013
Publication Date
August 1, 1983
Publication Information
Publication: Invest., Develop., and Evaluation of Performance Proving for Fault-Tolerant Computers
Subject Category
Computer Programming And Software
Accession Number
84N25323
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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