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Modeling "Soft" Errors in Bipolar Integrated CircuitsMathematical models represent single-event upset in bipolar memory chips. Physics of single-event upset in integrated circuits discussed in theoretical paper. Pair of companion reports present mathematical models to predict critical charges for producing single-event upset in bipolar randomaccess memory (RAM) chips.
Document ID
19850000158
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Zoutendyk, J. (Caltech)
Benumof, R. (Caltech)
Vonroos, O. (Caltech)
Date Acquired
August 12, 2013
Publication Date
October 1, 1985
Publication Information
Publication: NASA Tech Briefs
Volume: 9
Issue: 2
ISSN: 0145-319X
Subject Category
Electronic Components And Circuits
Report/Patent Number
NPO-16375
NPO-16293
NPO-16384
Accession Number
85B10158
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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