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The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithmRealization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes often requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.
Document ID
19850030436
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Hsu, I.-S. (University of Southern California Los Angeles, CA, United States)
Reed, I. S. (University of Southern California Los Angeles, CA, United States)
Wang, K. (University of Southern California Los Angeles, CA, United States)
Yeh, C.-S. (Southern California, University Los Angeles, CA, United States)
Truong, T. K. (University of Southern California Los Angeles, CA, United States)
Deutsch, L. J. (California Institute of Technology, Jet Propulsion Laboratory, Pasadena CA, United States)
Date Acquired
August 12, 2013
Publication Date
October 1, 1984
Publication Information
Publication: IEEE Transactions on Computers
Volume: C-33
ISSN: 0018-9340
Subject Category
Electronics And Electrical Engineering
Accession Number
85A12587
Funding Number(s)
CONTRACT_GRANT: N00039-80-C-0641
CONTRACT_GRANT: AF-AFOSR-80-0151
CONTRACT_GRANT: NAS7-100
Distribution Limits
Public
Copyright
Other

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