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Satellite baseband processor test performance summaryA satellite baseband processor (BBP) has been developed for the NASA Lewis 30/20 GHz Satellite Communications Program. The BBP design, reported elsewhere, has been implemented in a proof-of-concept (POC) model. The results of the laboratory system tests of the POC are summarized. Bit error rate test results are presented for the FDM/TDMA communication system operating at 27.5, 110, and 550 Mbps over a variety of operating conditions. The results clearly demonstrate the applicability of baseband processing to future high capacity satellite communication system concepts. A brief description of the system concept, its function, and the role of the baseband processor are presented. The test conditions and means of simulation are also described. The methods of test evaluation and their significance in a system context are given.
Document ID
19850032283
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Shaneyfelt, J. T.
(Motorola, Inc. Scottsdale, AZ, United States)
Attwood, S. W.
(Motorola, Inc. Scottsdale, AZ, United States)
Carroll, D. R.
(Motorola, Inc. Communications Div., Scottsdale, AZ, United States)
Date Acquired
August 12, 2013
Publication Date
January 1, 1983
Subject Category
Communications And Radar
Meeting Information
Meeting: EASCON ''83
Location: Washington, DC
Start Date: September 19, 1983
End Date: September 21, 1983
Accession Number
85A14434
Funding Number(s)
CONTRACT_GRANT: NAS3-22502
Distribution Limits
Public
Copyright
Other

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