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A VLSI design of a pipeline Reed-Solomon decoderA pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.
Document ID
19850052026
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Shao, H. M.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Truong, T. K.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Yuen, J. H.
(California Institute of Technology, Jet Propulsion Laboratory, Pasadena CA, United States)
Reed, I. S.
(Southern California, University Los Angeles, CA, United States)
Date Acquired
August 12, 2013
Publication Date
May 1, 1985
Publication Information
Publication: IEEE Transactions on Computers
Volume: C-34
ISSN: 0018-9340
Subject Category
Computer Operations And Hardware
Accession Number
85A34177
Funding Number(s)
CONTRACT_GRANT: NAS7-100
Distribution Limits
Public
Copyright
Other

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