NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Back to Results
VLSI architectures for computing multiplications and inverses in GF(2m)Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.
Document ID
19850060622
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Wang, C. C.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Truong, T. K.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Shao, H. M.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Deutsch, L. J.
(California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)
Omura, J. K.
(California, University Los Angeles, United States)
Date Acquired
August 12, 2013
Publication Date
August 1, 1985
Publication Information
Publication: IEEE Transactions on Computers
Volume: C-34
ISSN: 0018-9340
Subject Category
Computer Operations And Hardware
Accession Number
85A42773
Distribution Limits
Public
Copyright
Other

Available Downloads

There are no available downloads for this record.
No Preview Available