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Integrated-Circuit Active Digital FilterPipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.
Document ID
19860000020
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Nathan, R.
(Caltech)
Date Acquired
August 12, 2013
Publication Date
June 1, 1986
Publication Information
Publication: NASA Tech Briefs
Volume: 10
Issue: 1
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
NPO-16020
Accession Number
86B10020
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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