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Simulating Single-Event Upsets in Bipolar RAM'sSimulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.
Document ID
19860000025
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Zoutendyk, J. A.
(Caltech)
Date Acquired
August 12, 2013
Publication Date
June 1, 1986
Publication Information
Publication: NASA Tech Briefs
Volume: 10
Issue: 1
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
NPO-16491
Accession Number
86B10025
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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