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A VLSI single chip 8-bit finite field multiplierA Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.
Document ID
19860004993
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Deutsch, L. J. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Shao, H. M. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Hsu, I. S. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Truong, T. K. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 12, 2013
Publication Date
November 15, 1985
Publication Information
Publication: The Telecommunications and Data Acquisition Report
Subject Category
Electronics And Electrical Engineering
Accession Number
86N14463
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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