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The 1.2 micron CMOS technologyA set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.
Document ID
19860019790
Acquisition Source
Legacy CDMS
Document Type
Other
Authors
Pina, C. A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 12, 2013
Publication Date
June 1, 1985
Publication Information
Publication: Product Assurance Technology for Custom LSI(VLSI Electronics
Subject Category
Electronics And Electrical Engineering
Accession Number
86N29262
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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