VLSI Reed Solomon decoder designA Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80 Mbits/second. A total of seven chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.
Document ID
19870058449
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Maki, Gary K. (Idaho Univ. Moscow, ID, United States)
Owsley, Patrick A. (Idaho Univ. Moscow, ID, United States)
Cameron, Kelly B. (Idaho Univ. Moscow, ID, United States)
Venbrux, Jack (Idaho, University Moscow, United States)