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Single-Chip VLSI Reed-Solomon DecoderEfficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.
Document ID
19880000274
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Shao, Howard M.
(Caltech)
Truong, Trieu-Kie
(Caltech)
Hsu, In-Shek
(Caltech)
Deutsch, Leslie J.
(Caltech)
Date Acquired
August 13, 2013
Publication Date
May 1, 1988
Publication Information
Publication: NASA Tech Briefs
Volume: 12
Issue: 5
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
NPO-16854
Accession Number
88B10274
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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