NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Back to Results
Decoding of DBEC-TBED Reed-Solomon codesA problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256 K bit DRAM's are organized in 32 K x 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. The paper presents a special decoding technique for double-byte-error-correcting, triple-byte-error-detecting RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.
Document ID
19880030221
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Deng, Robert H.
(Notre Dame Univ. IN, United States)
Costello, Daniel J., Jr.
(Notre Dame, University IN, United States)
Date Acquired
August 13, 2013
Publication Date
November 1, 1987
Publication Information
Publication: IEEE Transactions on Computers
Volume: C-36
ISSN: 0018-9340
Subject Category
Computer Operations And Hardware
Accession Number
88A17448
Funding Number(s)
CONTRACT_GRANT: NAG2-202
Distribution Limits
Public
Copyright
Other

Available Downloads

There are no available downloads for this record.
No Preview Available