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Electronic hardware implementations of neutral networksThis paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom VLSI technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.
Document ID
19880035618
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Thakoor, A. P.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Moopenn, A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Lambe, John
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Khanna, S. K.
(California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)
Date Acquired
August 13, 2013
Publication Date
December 1, 1987
Publication Information
Publication: Applied Optics
Volume: 26
ISSN: 0003-6935
Subject Category
Cybernetics
Accession Number
88A22845
Distribution Limits
Public
Copyright
Other

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