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Noise-margin limitations on gallium-arsenide VLSITwo factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.
Document ID
19880061313
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Long, Stephen I.
(California Univ. Santa Barbara, CA, United States)
Sundaram, Mani
(California, University Santa Barbara, United States)
Date Acquired
August 13, 2013
Publication Date
August 1, 1988
Publication Information
Publication: IEEE Journal of Solid-State Circuits
Volume: 23
ISSN: 0018-9200
Subject Category
Electronics And Electrical Engineering
Accession Number
88A48540
Distribution Limits
Public
Copyright
Other

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