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Programmable Pipelined Image ProcessorA pipelined image processor selectively interconnects modules in a column of a two-dimensional array to modules of the next column of the array of modules 1,1 through M,N, where M is the number of modules in one dimension and N is the number of modules in the other direction. Each module includes two input selectors for A and B inputs, two convolvers, a binary function operator, a neighborhood comparison operator which produces an A output and an output selector which may select as a B output the output of any one of the components in the module, including the A output of the neighborhood comparison operator. Each module may be connected to as many as eight modules in the next column, preferably with the majority always in a different row that is up (or down) in the array for a generally spiral data path around the torus thus formed. The binary function operator is implemented as a look-up table addressed by the most significant 8 bits of each 12-bit argument. The table output includes a function value and the slopes for interpolation of the two arguments by multiplying the 4 least significant bits in multipliers and adding the products to the function value through adders.
Document ID
19890017029
Acquisition Source
Headquarters
Document Type
Other - Patent
External Source(s)
NPO-16461-1CU
Authors
Donald B Gennery
(Jet Propulsion Laboratory La Cañada Flintridge, United States)
Brian H Wilcox
(Jet Propulsion Laboratory La Cañada Flintridge, United States)
Date Acquired
August 13, 2013
Publication Date
December 6, 1988
Publication Information
Publisher: United States Patent and Trademark Office
Subject Category
Computer Operations And Hardware
Accession Number
89N26400
Funding Number(s)
CONTRACT_GRANT: NAS7-918
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-4,790,026
Patent Application
US-PATENT-APPL-SN-815103
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