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Impact of device level faults in a digital avionic processorThis paper describes an experimental analysis of the impact of gate and device-level faults in the processor of a flight control system. Via mixed mode simulation faults were injected both at the gate (stuck-at) and at the transistor levels, and their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model insofar as error activity or detection within a functional unit is concerned. Insofar as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other, although the stuck-at model overestimates, by over one hundred percent, the probability of fault propagation to the output pins. The stuck-at model significantly underestimates the impact of an internal chip fault on the output pins.
Document ID
19890030741
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Kim, S.
(Illinois Univ. Urbana, IL, United States)
Iyer, R. K.
(Illinois, University Urbana, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1988
Subject Category
Aircraft Instrumentation
Report/Patent Number
AIAA PAPER 88-3904
Meeting Information
Meeting: AIAA/IEEE Digital Avionics Systems Conference
Location: San Jose, CA
Country: United States
Start Date: October 17, 1988
End Date: October 20, 1988
Accession Number
89A18112
Funding Number(s)
CONTRACT_GRANT: NAG1-602
Distribution Limits
Public
Copyright
Other

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