CMOS Process MonitorA CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.
Document ID
19890044953
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Buehler, M. G. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Allen, R. A. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Blaes, B. R. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Jenings, G. A. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Hicks, K. A. (California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)