A methodology based on reduced complexity algorithm for system applications using microprocessorsThe paper considers a methodology on the analysis and design of a minimum mean-square error criterion linear system incorporating a tapped delay line (TDL) where all the full-precision multiplications in the TDL are constrained to be powers of two. A linear equalizer based on the dispersive and additive noise channel is presented. This microprocessor implementation with optimized power of two TDL coefficients achieves a system performance comparable to the optimum linear equalization with full-precision multiplications for an input data rate of 300 baud.
Document ID
19890058771
Acquisition Source
Legacy CDMS
Document Type
Conference Proceedings
Authors
Yan, T. Y. (California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)
Yao, K. (California, University Los Angeles, United States)