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Multi-level Hierarchical Poly Tree computer architecturesBased on the concept of hierarchical substructuring, this paper develops an optimal multi-level Hierarchical Poly Tree (HPT) parallel computer architecture scheme which is applicable to the solution of finite element and difference simulations. Emphasis is given to minimizing computational effort, in-core/out-of-core memory requirements, and the data transfer between processors. In addition, a simplified communications network that reduces the number of I/O channels between processors is presented. HPT configurations that yield optimal superlinearities are also demonstrated. Moreover, to generalize the scope of applicability, special attention is given to developing: (1) multi-level reduction trees which provide an orderly/optimal procedure by which model densification/simplification can be achieved, as well as (2) methodologies enabling processor grading that yields architectures with varying types of multi-level granularity.
Document ID
19900039027
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Padovan, Joe
(Akron Univ. Akron, OH, United States)
Gute, Doug
(Akron, University OH, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1990
Publication Information
Publication: Computers and Structures
Volume: 34
Issue: 5 19
ISSN: 0045-7949
Subject Category
Computer Programming And Software
Accession Number
90A26082
Funding Number(s)
CONTRACT_GRANT: NAG3-664
Distribution Limits
Public
Copyright
Other

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