Single chip fixed frequency bit synchronizerA single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.
Document ID
19900041833
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Butler, Madeline J. (NASA Goddard Space Flight Center Greenbelt, MD, United States)
James, Calvin L. (Bendix Field Engineering Corp. Columbia, MD, United States)