Analysis of hypercube cache performance using address traces generated by TRAPEDSThe authors utilize a recently developed software method of capturing and analyzing address traces, known as TRAPEDS (TRAce Producing Execution Driven Simulation), to provide address traces for cache performance evaluation on a hypercube multicomputer. Utilizing TRAPEDS user code traces obtained from the implementations of several parallel algorithms on the Intel iPSC/2 hypercube, the authors simulate the cache performance effects of changing cache size, line size, and set associativity. Particular attention is devoted to the effect on cache performance of changing the dimension of the hypercube for a particular program and to the variation in cache statistics among the nodes of the hypercube.
Document ID
19900050400
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Stunkel, Craig B. (Illinois Univ. Urbana, IL, United States)
Fuchs, W. Kent (Illinois, University Urbana, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1989
Subject Category
Computer Programming And Software
Meeting Information
Meeting: 1989 International Conference on Parallel Processing