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Programmable synaptic devices for electronic neural netsThe architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.
Document ID
19900052864
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Moopenn, A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Thakoor, A. P.
(JPL Pasadena, CA, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1990
Publication Information
Publication: Control and Computers
Volume: 18
Issue: 2, 19
ISSN: 0315-8934
Subject Category
Electronics And Electrical Engineering
Accession Number
90A39919
Distribution Limits
Public
Copyright
Other

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