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Testing interconnected VLSI circuits in the Big Viterbi DecoderThe Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.
Document ID
19910022951
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Onyszchuk, I. M.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
September 6, 2013
Publication Date
August 15, 1991
Publication Information
Publication: The Telecommunications and Data Acquisition Report
Subject Category
Electronics And Electrical Engineering
Accession Number
91N32265
Funding Number(s)
PROJECT: RTOP 310-30-72-88-01
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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