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Simulated fault injection - A methodology to evaluate fault tolerant microprocessor architecturesA simulation-based fault-injection method for validating fault-tolerant microprocessor architectures is described. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time to assess the resulting fault impact. As an example, a fault-tolerant architecture which models the digital aspects of a dual-channel real-time jet-engine controller is used. The level of effectiveness of the dual configuration with respect to single and multiple transients is measured. The results indicate 100 percent coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.
Document ID
19910030307
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Choi, Gwan S.
(Illinois Univ. Urbana, IL, United States)
Iyer, Ravishankar K.
(Illinois, University Urbana, United States)
Carreno, Victor A.
(NASA Langley Research Center Hampton, VA, United States)
Date Acquired
August 15, 2013
Publication Date
October 1, 1990
Publication Information
Publication: IEEE Transactions on Reliability
Volume: 39
ISSN: 0018-9529
Subject Category
Computer Programming And Software
Accession Number
91A14930
Funding Number(s)
CONTRACT_GRANT: NAG1-602
Distribution Limits
Public
Copyright
Other

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