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An 8-b 1.3-MHz successive-approximation A/D converterA new successive-approximation A/D converter is described. It combines a string of equal-valued polysilicon resistors and a set of ratioed capacitors in a unique circuit configuration so that a high sampling rate is achieved. The comparator is realized by a chopper-stabilized amplifier to reduce the effect of the offset voltages of MOS amplifiers. The converter performs an 8-b monotonic conversion with a differential nonlinearity less than 1 LSB in 770 nsec. The die area is 3750 sq mil. This new conversion technique can also be utilized in a pipelined A/D converter (Temes, 1985) and enables it to achieve high speed.
Document ID
19910034975
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Hadidi, KH.
(California Univ. Los Angeles, CA, United States)
Tso, Vincent S.
(California Univ. Los Angeles, CA, United States)
Temes, Gabor C.
(California, University Los Angeles, United States)
Date Acquired
August 15, 2013
Publication Date
June 1, 1990
Publication Information
Publication: IEEE Journal of Solid-State Circuits
Volume: 25
ISSN: 0018-9200
Subject Category
Electronics And Electrical Engineering
Accession Number
91A19598
Funding Number(s)
CONTRACT_GRANT: NCC2-374
Distribution Limits
Public
Copyright
Other

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