Competitive neural architecture for hardware solution to the assignment problem

The architecture for competitive assignment is described with attention given to the VLSI design and critical circuits fabricated in complementary metal-oxide semiconductor. The local application of association costs to processing units reduces the connectivity to the number of VLSI-compatible processing units. 'Hysteretic annealing' is discussed and when compared to mean-field annealing is found to enhance processing-unit gain and provide near-optimal solutions in about 150 microsec.