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Low-Jitter Digital Rate MultiplierJitter in digital rate multiplier reduced by improved method involving use of two slightly different minor clock periods. Original application to divide measured period of spin of spacecraft into large number of equal subintervals, by counting cycles of master oscillator running at high frequency. Method also used to reduce jitter in other situations necessary to generate equal subintervals from synchronizing clock signal of arbitrary period. Particularly valuable in situations where synchronizing signals lost temporarily and where drift in analog circuit unacceptable.
Document ID
19930000320
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Katz, Richard B.
(NASA Goddard Space Flight Center, Greenbelt, MD.)
Rakow, Glenn P.
(NASA Goddard Space Flight Center, Greenbelt, MD.)
Date Acquired
August 16, 2013
Publication Date
June 1, 1993
Publication Information
Publication: NASA Tech Briefs
Volume: 17
Issue: 6
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
GSC-13545
Accession Number
93B10320
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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