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Low power SEU immune CMOS memory circuitsThe authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.
Document ID
19930051043
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Liu, M. N.
(NASA Headquarters Washington, DC United States)
Whitaker, Sterling
(NASA Space Engineering Research Center for VLSI System Design; Idaho Univ. Moscow, United States)
Date Acquired
August 16, 2013
Publication Date
December 1, 1992
Publication Information
Publication: IEEE Transactions on Nuclear Science
Volume: 39
Issue: 6 pt
ISSN: 0018-9499
Subject Category
Electronics And Electrical Engineering
Accession Number
93A35040
Funding Number(s)
CONTRACT_GRANT: NAGW-1406
Distribution Limits
Public
Copyright
Other

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