The application of multiple instruction retry to VLIW architectures using compiler generated hazard-free code

In this paper, we describe the development of compiler assisted multiple instruction word retry for VLIW architectures. Compiler generated hazard-free code with different degrees of rollback capability is compacted by a trace scheduling algorithm. Performances are compared under three parameters: N, the rollback distance for uni-processors; P, the number of functional units; and Np, the rollback distance for VLIW architectures. In the majority of benchmarks examined, for fixed P and Np, the larger N tends to generate compacted code with better performance.