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CCSDS Reed Solomon VLSI chip setA highly efficient error correcting code has been selected by NASA as a CCSDS standard: the 16 symbol error correcting Reed Solomon code. A VLSI implementation of this decoder is described in this paper. A total of 4 full custom VLSI chips are needed that correct data in real time at an sustained rate of up to 80 Mbits/second.
Document ID
19940004322
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Cameron, K. (Idaho Univ. Moscow, ID, United States)
Whitaker, S. (Idaho Univ. Moscow, ID, United States)
Liu, N. (Idaho Univ. Moscow, ID, United States)
Liu, K. (Idaho Univ. Moscow, ID, United States)
Canaris, J. (Idaho Univ. Moscow, ID, United States)
Date Acquired
August 16, 2013
Publication Date
January 24, 1990
Publication Information
Publication: The First NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N71077
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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IDRelationTitle19940004319Collected WorksNASA SERC 1990 Symposium on VLSI Design
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