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Reed Solomon error correction for the space telescopeThis paper reports a single 8.2mm by 8.4mm, 200,000 transistor CMOS chip implementation of the Reed Solomon code required by the Space Telescope. The chip features a 10 MHz sustained byte rate independent of error pattern. The 1.6 micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with programmable corrections of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors.
Document ID
19940004323
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Whitaker, S.
(Idaho Univ. Moscow, ID, United States)
Cameron, K.
(Idaho Univ. Moscow, ID, United States)
Canaris, J.
(Idaho Univ. Moscow, ID, United States)
Vincent, P.
(Idaho Univ. Moscow, ID, United States)
Liu, N.
(Idaho Univ. Moscow, ID, United States)
Owsley, P.
(Idaho Univ. Moscow, ID, United States)
Date Acquired
August 16, 2013
Publication Date
January 24, 1990
Publication Information
Publication: The First NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N71078
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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