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Implementation and Performance of GaAs Digital Signal Processing ASICsThe feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.
Document ID
19970014227
Acquisition Source
Jet Propulsion Laboratory
Document Type
Reprint (Version printed in journal)
Authors
Whitaker, William D.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Buchanan, Jeffrey R.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Burke, Gary R.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Chow, Terrance W.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Graham, J. Scott
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Kowalski, James E.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Lam, Barbara
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Siavoshi, Fardad
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Thompson, Matthew S.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Johnson, Robert A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA United States)
Date Acquired
August 17, 2013
Publication Date
May 1, 1993
Publication Information
Publisher: Institute of Electrical and Electronics Engineers
ISSN: 0-7803-1375
Subject Category
Communications And Radar
Report/Patent Number
NASA-CR-203517
NAS 1.26:203517
Accession Number
97N71137
Funding Number(s)
CONTRACT_GRANT: NAS7-900
Distribution Limits
Public
Copyright
Public Use Permitted.
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