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Single event upset susceptibility testing of the Xilinx Virtex II FPGAHeavy ion testing of the Xilinx Virtex IZ was conducted on the configuration, block RAM and user flip flop cells to determine their single event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA is used to reveal L1/e values and single-event-functional interrupt failures.
Document ID
20060030120
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Yui, C.
Swift, G.
Carmichael, C.
Date Acquired
August 23, 2013
Publication Date
September 10, 2002
Distribution Limits
Public
Copyright
Other
Keywords
FPGA Xilinx Virtex static test single event upset

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