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Effect of thermal cycling ramp rate on CSP assembly reliabilityA JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.
Document ID
20060031143
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Ghaffarian, R.
Date Acquired
August 23, 2013
Publication Date
May 29, 2001
Distribution Limits
Public
Copyright
Other
Keywords
accelerated thermal cycle chip scale package solder joint reliability CSP BGA

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